Power management is an integral part of system-on-chip (SoC) design. Effective energy management for an SoC requires strategic planning at every processing stage, beginning at the architecture design stage. In a continuous effort to reduce power density, assimilating techniques to optimize low-power consumption in an integrated circuit is useful at every stage of the design. As technology moves towards more complex integrated circuit designs, for example, three-dimensional integrated circuit design, providing gated module layouts for multi-power domains becomes increasingly complex.
In a low-power SoC design, power-gated (on/off) and pre-gated (always on) logic can initially co-exist on an integrated circuit tile nested together in the same area. In this example, a default power supply rail is associated with the power-gated domain, and a secondary power supply rail is associated with the pre-gated power domain. The nested pre-gated power domain logic cells are primarily power control circuitry or feedthroughs. Electronic design automation (EDA) place-and-route tools place instances of logic circuitry in an integrated circuit design. However, typically, EDA place-and-route tools are not power grid aware. Instead, they place pre-gated domain instances at locations based on timing and congestion alone and tend to scatter them throughout the integrated circuit tile. Consequently, during legalization of an integrated circuit design layout the placement of pre-gated instances may result in a location that cannot be powered by the secondary rail.
Clustering is a method to assist the EDA place-and-route tool to route power to nested pre-gated logic instances. Clustering works well when small amounts of pre-gated logic are scattered across an integrated circuit tile. However, as the relative area of pre-gated domain logic increases with respect to the power-gated domain logic, this known clustering technique fails to allow the EDA place-and-route tool to satisfy routing requirements. For example, the existing clustering technique tends to create centralized power islands, and when a large number of cells are involved, the design may become unrouteable and the layout unusable.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.